posted Nov 3, 2016, 7:35 PM by Khaled salama
updated Nov 3, 2016, 7:58 PM
Abdulaziz demnostrates the lowest reported Figure of Merit of 45.8fJ/step capacitance to Digital converter. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. For more details check
This work builds on our earlier work:
- Hesham Omran, Muhammad Arsalan and Khaled N. Salama, An Integrated Energy-Efficient Capacitive Sensor Digital Interface Circuit, Sensors and Actuators A: Physical, Volume 216, Pages 43–51, 2014
- H. Omran, M. Arsalan, and K. N. Salama, “A robust parasitic-insensitive successive approximation capacitance-to-digital converter,” IEEE Custom Integrated Circuits Conference (CICC), 2014.
- H. Omran, H. Alahmadi, and K. N. Salama, “Matching properties of femtofarad and sub-femtofarad MOM capacitors,” IEEE Transactions on Circuits and Systems I, 2016
- Hesham Omran, Rami T. ElAfandy, Muhammad Arsalan, and Khaled N. Salama, Direct Mismatch Characterization of femto-Farad Capacitors, IEEE transactions on circuits and systems II, vol 63, no 2, pp. 151-155, 2016. (DOI:10.1109/TCSII.2015.2468919)
Follow up work:
- H. Omran, A. Alhoshany, H. Alahmadi , and K. N. Salama, “A 35fJ/Step Differential Successive Approximation Capacitive Sensor Readout Circuit with Quasi-Dynamic Operation,” Symposia on VLSI Technology and Circuits, 2016.
- H. Omran, Abdulaziz Alhoshany, H. Alahmadi, and K. N. Salama, A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers" IEEE Transactions on Circuits and Systems I, 2016