posted Nov 18, 2016, 12:56 PM by Khaled salama
updated Nov 18, 2016, 3:58 PM
A 12 − bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is demonstrated based on a chain of cascode inverter-based amplifiers with near-threshold biasing. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/◦C is achieved without the need for calibration. The work has been accepted at IEEE transactions on circuits and systems.
Its worth mentioning that a differential version of the work has been presented at the prestigious VLSI symposium with almost the same FoM due the use of Quasi-dynamic operation to maintain the energy efficiency for a scalable sample rate
This work builds on our earlier work:
- Hesham Omran, Muhammad Arsalan and Khaled N. Salama, An Integrated Energy-Efficient Capacitive Sensor Digital Interface Circuit, Sensors and Actuators A: Physical, Volume 216, Pages 43–51, 2014
- H. Omran, M. Arsalan, and K. N. Salama, “A robust parasitic-insensitive successive approximation capacitance-to-digital converter,” IEEE Custom Integrated Circuits Conference (CICC), 2014.
- H. Omran, H. Alahmadi, and K. N. Salama, “Matching properties of femtofarad and sub-femtofarad MOM capacitors,” IEEE Transactions on Circuits and Systems I, 2016
- Hesham Omran, Rami T. ElAfandy, Muhammad Arsalan, and Khaled N. Salama, Direct Mismatch Characterization of femto-Farad Capacitors, IEEE transactions on circuits and systems II, vol 63, no 2, pp. 151-155, 2016. (DOI:10.1109/TCSII.2015.2468919)
- Abdulaziz Alhoshany, Hesham Omran, Khaled N. Salama, "A 45.8fJ/Step, Energy-Efficient, Differential SAR Capacitance-to-Digital Converter for Capacitive Pressure Sensing", Sensors & Actuators: A. Physical, Vol 245, Pages 10–18, 2016