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Future Generation Computing Systems made possible at KAUST

posted Oct 24, 2014, 11:24 AM by Khaled salama   [ updated Jul 24, 2015, 6:30 AM ]
Conventional computing based on Von Neumann architecture has been shown to be approaching its limits in scalability and power consumption.  If solved with contemporary machines, today’s applications in science and industry related to data analysis, pattern recognition and prediction would demand a huge computing power. In the era of ubiquitous sensing and data acquisition, a way to cheaply and power efficiently make sense of the collected ‘big data’ is of utmost importance. Here, human brain’s efficiency becomes the ultimate standard and inspiration for any future technology. Currently we need approximately 83,000 powerful processors to run for 40 minutes to simulate one second of brain activity with multiple orders of magnitude more power.

Such trend of understanding the brain behavior is currently gaining a huge attention worldwide. The European Union for example selected the "Human Brain Project"  as European Flagship to reverse engineer the biological brain down to the molecular level.  This project will accrue a fund of 1.19 billion euros over a period of ten years. Another example is the United States project: “Brain Research through Advancing Innovative Neurotechnologies (BRAIN)”  ( aka: Obama Brain Project). This project started in 2014 with an initial fund of 300 million USD paid by NIH (National Institute of Health). The last example is DARPA’s “SyNAPSE: Systems of Neuromorphic Adaptive Plastic Scalable Electronics”  project attempting to build a computer with similar form, function, and architecture to the mammalian brain. An example of is the IBM’s bra in-inspired chip to transform mobility and Internet of Things through sensory perception. 
At the sensors lab, students under the supervision of Prof. K.N. Salama are exploring new computing technologies miming the way our brains process and store data. In particular, the work of PhD student Mohammed Zidan on memristors and Resistive memory arrays (ReRAM) is of great significance.  ReRAM potentially address many of the challenges facing such a task. Using memristors to build neural networks reduces the required area significantly compared to classical circuits. ReRAM have also gained a lot of interest with the announcement of "The Machine" , a server technology recently introduced by HP fusing memory and storage through the use of resistive memories to form a one flat memory hierarchy.  Resistive memory devices are very promising candidates replace the current storage technologies, due to their very high density, fast access time, and retainability. However, there are numerous challenges that need to be addressed before memristor devices genuinely replace the current technologies.

In two recent papers at the prestigious IEEE Transaction on Nanotechnology (TNANO), we show how to solve some of the challenges facing such huge and flat memory array.  We introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings. The new method requires fewer reading steps compared to previously reported techniques by HP, and has a very small impact on the memory density. We further extend the work to gated arrays that were thought to solve the sneak path problem. We show that leakage current ruins the memory readout process for high-density gated arrays, and analyze the trade-off between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage current effect.

3D illustrations and equivalent circuits for (a,b) gateless 
memristor memory cell and
 (c,d) gated memristor memory cell

This work is described in detail in our recent two articles at IEEE TNANO that were highly praised by the reviewers:

1. M. Affan Zidan, H. Omran, A. Sultan, H. A. H. Fahmy, and K. N. Salama  Compensated Readout for High Density MOS-Gated MemristorCrossbar Array  IEEE Transaction on Nanotechnology (TNANO), vol. 14, no. 1, pp. 1-4, Jan 2015

2. M. A. Zidan, H. Fahmy, A. Eltawil, F. Kurdahi and K. N. Salama Memristor Multi-Port Readout: A Closed-FormSolution for Sneak-Paths  IEEE Transactions on Nanotechnology (TNANO), vol.13, no.2, pp.274-282, March 2014 

This work builds on our earlier widely cited Survey paper on Memristor Based Memory: The Sneak Paths Problem and Solutions that is recognized by ScienceDirect as one of the Top 25 hottest papers published in Microelectronics Journal in the period (January-March) and (April-June). The Top 25 provides lists of most read articles - counted by article downloads on ScienceDirect