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Mohammed Asadullah Khan


Asad enrolled at KAUST in the Fall of 2013 as a PhD student. Prior to joining KAUST, Asad worked at Intel Labs for 3 years as a Design Engineer. His Masters project titled 'Experimental Investigation of Quantum Effects in Ultra-Thin Films of Monocrystalline Silicon', involved fabrication of ultra-thin silicon films(< 10nm thick), making pseudo MOSFET devices on these films, taking optical measurements of films, modeling optical constraints using a mathematical model utilizing the Kramers Kronig relationship. While working at Intel lab, he did a variety of tasks eg. hardening flops for sub-threshold operation, full chip power validation, design and logical verification of network-on-chip for an ultra efficient exascale compute system, front end SoC integration, full chip formal verification. He has designed chips for Intel's 32nm, 22nm and 14nm SoC processes. 

Research interests:
As a part of his academic and professional work, he has been fortunate to gain exposure to a wide range of tools and techniques used in the VLSI industry such as Modelsim, VCS, Sentaurus, coreBuilder, coreAssembler, coreConsultant,  Design Compiler, HSpice, PrimeTime, Formality, Conformal, oxidation furnaces, wet bench, ellipsometer, reflectometer, litho bench, laser writer, C-V meter, I-V meter, Probe Station, 4 point resistivity probe, photoluminescence meter, Raman Spectrometer, AFM, SEM, thermal evaporator, RF sputtering, ALD. Asad is proficient in most Hardware Descriptive Languages (VHDL, Verilog, System Verilog), Python, Matlab and Mathematica.


Education background:
  • M.E. (Microelectronic Systems), Indian Institute of Science, Bangalore, India (Winner of Alumni Medal for excellence in academics)
  • B.E. (Electronics and Communication), Osmania University, Hyderabad, India (1st Rank)
Selected publications:
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