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Stochastic memristor model

We developed a stochastic model of memristor devices.  Innate stochasticity is modeled in a circuit compatible format and incorporated into models of threshold based memristors covering a wide set of designs.  Experimental fitting to fabricated devices highlights the modeling accuracy and the generalized form of behavior. 

Feel free to use/modify these codes as you see fit. Any publications  (codes, papers, technical reports,..) in which our codes (in their original or a modified format) have been used should cite the following references.     

References:                                                             

 [1]      Rawan Naous, Maruan Al-Shedivat, and Khaled Nabil Salama, Stochasticity Modeling in MemristorsIEEE Transactions on Nanotechnology (TNANO), vol. 15, no. 1, pp. 15-28, 2016 DOI:10.1109/TNANO.2015.2493960

[2]      Maruan Al-Shedivat, Rawan Naous,Gert Cauwenberghs, and Khaled Nabil Salama, Memristors Empower Spiking Neurons with Stochasticity, IEEE Journal of Emerging technologies in circuits and systems, VOL. 5, NO. 2, 242-253, JUNE 2015        

Copyright (c) 2015, Rawan Naous, Maruan Al-Shedivat, Khaled Nabil Salama                   
King Abdullah University of Science and Technology
All rights reserved.
Last Update: 9-Nov-2015; run using run using spectre version 11.1.0.509.isr    cadence version 2012.09                                     
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stochastic_memristor.va
(12k)
Khaled salama,
Nov 9, 2015, 2:50 AM
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stochasticity_test.scs
(6k)
Khaled salama,
Nov 9, 2015, 2:51 AM
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