FPGA

Generalized Hardware Post Processing Technique for Chaos-Based Pseudorandom Number Generators

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Mohamed L. Barakat, et al., "Generalized Hardware Post Processing Technique for Chaos-Based Pseudorandom Number Generators" ETRI Journal, 35, (3), 2013, 448. Abstract: This paper presents a generalized post‐processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR‐based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third‐order chaotic system with maximum function nonlinearity is

Hesham Omran wins the first phase of the 8th Annual International Microelectronics Olympiad of Armenia

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Hesham Omran, a PhD student in Prof Khaled Salama's research group (Sensors Lab) won the the first phase of the 8th Annual International Microelectronics Olympiad of Armenia.

Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure Detection

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Heba Elhosary, et al., "Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure Detection." IEEE Transactions on Biomedical Circuits and Systems 13 (6), 2019, 1324. In this paper, a low power support vector machine (SVM) training, feature extraction, and classification algorithm are hardware implemented in a neural seizure detection application. The training algorithm used is the sequential minimal optimization (SMO) algorithm. The system is implemented on different platforms: such as field programmable gate array (FPGA), Xilinx Virtex-7 and

FPGA Implementation of Dynamically Reconfigurable IoT security Module Using Algorithm Hopping

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Shady Soliman, et al., "FPGA Implementation of Dynamically Reconfigurable IoT security Module Using Algorithm Hopping." Integration 68, 2019, 108. Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS

EANN: Energy Adaptive Neural Networks

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Salma Hassan, et al., "EANN: Energy Adaptive Neural Networks." Electronics 9 (5), 2020, 746. This paper proposes an Energy Adaptive Feedforward Neural Network (EANN). It uses multiple approximation techniques in the hardware implementation of the neuron unit. The used techniques are precision scaling, approximate multiplier, computation skipping, neuron skipping, activation function approximation and truncated accumulation. The proposed EANN system applies the partial dynamic reconfiguration (PDR) feature supported by the FPGA platform to reconfigure the hardware elements of the neural network

Hesham Omran

Research Staff, Sensors
Hesham Omran worked as a Researcher with the Sensors Lab after obtaining his Ph.D. degree in Electrical Engineering under the supervision of Prof. Khaled Nabil Salama from King Abdullah University of Science and Technology (KAUST), Thuwal, Kingdom of Saudi Arabia. He received the B.Sc. (with honors) and M.Sc. degrees from Ain Shams University, Cairo, Egypt, in 2007 and 2010, respectively, both in electrical engineering. From 2008 to 2011, he was a Research and Teaching Assistant with the Integrated Circuits Lab (ICL), Ain Shams University, and a Design Engineer with Si-Ware Systems (SWS)

Abdurauf Abdurakhmanov