CMOS

An integrated energy-efficient capacitive sensor digital interface circuit

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Hesham Omran, et al., "An integrated energy-efficient capacitive sensor digital interface circuit." Sensors and Actuators A: Physical 216, 2014, 43. In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to achieve parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not

A 7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

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Hesham Omran, et al., "7.9 pJ/step energy-efficient multi-slope 13-bit capacitance-to-digital converter." IEEE Transactions on Circuits and Systems II: Express Briefs 61 (8), 2014, 589. In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for

A low‐power 802.11 ad compatible 60‐GHz phase‐locked loop in 65‐nm CMOS

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Hammad M. Cheema, et al., "A low‐power 802.11 ad compatible 60‐GHz phase‐locked loop in 65‐nm CMOS" Microwave and Optical Technology Letters 57 (3), 2015, 660. A 60‐GHz fundamental frequency phase locked loop (PLL) as part of a highly integrated system‐on‐chip transmitter with on‐chip memory and antenna is presented. As a result of localized optimization approach for each component, the PLL core components only consume 30.2 mW from a 1.2 V supply. A systematic design procedure to achieve high phase margin and wide locking range is presented. The reduction of parasitic and fixed capacitance

Wide-range adaptive RF-to-DC power converter for UHF RFIDs

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Mahmoud H. Ouda, et al., "Wide-range adaptive RF-to-DC power converter for UHF RFIDs." IEEE Microwave and Wireless Components Letters 26 (8), 2016, 634. A wide-range, differential, cross-coupled rectifier is proposed with an extended dynamic range of input RF power that enables wireless powering from varying distances. The proposed architecture mitigates the reverse-leakage problem in conventional, cross-coupled rectifiers without degrading sensitivity. A prototype is designed for UHF RFID applications, and is implemented using 0.18 μm CMOS technology. On-chip measurements demonstrate a

Experimental behavior evaluation of series and parallel connected constant phase elements

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Georgia Tsirimokou, et al., "Experimental behavior evaluation of series and parallel connected constant phase elements". AEU-International Journal of Electronics and Communications, 74, 2017, 5. Fractional-order capacitors are the core building blocks for implementing fractional-order circuits. Due to the absence of their commercial availability, they can be approximated through appropriately configured passive or active integer-order element topologies. Such a topology, constructed using Operational Transconductance Amplifiers (OTAs) and capacitors has been implemented in monolithic form

A biosensor-CMOS platform and integrated readout circuit in 0.18-μm CMOS technology for cancer biomarker detection

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Abdulaziz Alhoshany, et al., " A biosensor-CMOS platform and integrated readout circuit in 0.18-μm CMOS technology for cancer biomarker detection". Sensors, 17(9), 2017, 1942. This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor

CMOS-RC Colpitts oscillator design using floating fractional-order inductance simulator

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Kartci, Aslihan, et al. "CMOS-RC Colpitts oscillator design using floating fractional-order inductance simulator." IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018, 905. This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75 th order Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CF±s), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic

Analog backpropagation learning circuits for memristive crossbar neural networks

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Krestinskaya, Olga, "Analog backpropagation learning circuits for memristive crossbar neural networks." 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2018, 1. The implementation of backpropagation algorithm using gradient descent operation with analog circuits is an open problem. In this paper, we present the analog learning circuits for realizing backpropagation algorithm for use with neural networks in memristive crossbar arrays. The circuits are simulated in SPICE using TSMC 180nm CMOS process models, and HP memristor models. The gradient descent operations are